1. Field of the Invention
The present invention generally relates to a non-volatile memory cell with its operations, and more particularly to a non-volatile memory cell suitable for flash and byte operation application.
2. Description of the Prior Art
Semiconductor based memory devices largely comprises Random Access Memories (RAM) and Read Only Memory (ROM). RAM is referred to as volatile memory, in that when supply voltage is removed, data is destroyed with the passage of time. ROM devices, including Programmable ROM (PROM), Erasable PROM (EPROM), and Electrically EPROM (EEPROM). Numerous EEPROM cells and flash memory cells can be simultaneously erased, and are characterized by a stacked gate structure comprising a floating gate and a control gate.
The conventional P-channel stacked gate flash cell programming operation is utilized the channel hot hole induces the hot electron to put the electron into the floating gate. Furthermore, erasing operation is utilized FN (Fowler-Nordheim) tunneling through the tunneling oxide by FN tunneling to pull out the electron from the floating gate to the substrate. Accordingly, the programming operation is byte operation but the erasing operation is not.
FIG. 1 shows a conventional EEPROM cell 100 in which more than two binary states may be represented by programming cell 100's threshold voltage to one of many predetermined levels. When the EEPROM cell 100 is read, the current level conducted therein is dependent upon the threshold voltage thereof.
EEPROM cell 100 includes a storage transistor 104 and a select transistor 106 that are formed in a P-type substrate 102. N+ diffusion region 108 serves as the source of storage transistor 104. N+ diffusion region 110 serves as the drain of the storage transistor 104 as well as the source for select transistor 106, and N+ diffusion 112 serves as the drain of select transistor 106. A bit line, BL, of an associated memory array (not shown in FIG. 1) is coupled to the drain 112 of select transistor 106. A high impedance resistor 122 is coupled between the drain 112of select transistors 106 and ground potential. Storage transistor 104 has an interpoly dielectric layer 118 between the floating gate 116 and a control gate 120, and a select transistor 106 has a select gate 122. A tunneling window is formed within the tunneling oxide layer 114 of facilitate electron high voltage between floating gate 116 and the drain 110.
Floating gate 116 is charged by applying an erase voltage VE between 16 through 20 volts to the control gate 120, applying 16 through 20 volts to the select gate 122, and applying 0 volt to the bit line, and source region 108 is floating. Electrons of the tunneling oxide layer float from the drain region 110 to the floating gate 116, thereby the threshold voltage Vt of the storage transistor 104 can be increased.
The EEPROM cell 100 may be programmed by applying a program voltage Vpp between 13–20 volts to the bit line and the select gate 122 while the control gate 120 is grounding, and the source region 108 is in a high impedance state. The resultant electrical field causes the electrons of the tunneling oxide layer that floats from the floating gate 116 to the drain region 112, thereby the floating gate 116 is discharged, and the threshold voltage Vt of the EEPROM cell 100 is decreased. Thus, the current is conducted by the EEPROM cell 100 during a read operation that may be controlled by adjusting the program voltage Vpp.
Erase take place electrically by F-N tunneling of electrons from the floating gate to the source (source erase) to the channel region (channel erase). During the electrical erasing operation, an field oxide layer on the order of 10 MV/cm is generated across the thin oxide between the floating gate and the n+ source diffusion (or the channel). This is accomplished by the three types erasing methods. The extent of cell erasure is controlled by circuitry, and is done algorithmically by using a series of erasing and erasing verifies operation. Each erase pulse is typically 10 ms in length and is followed by a verification of the erased threshold by sensing the cell current.
One of the erasing methods is grounded gate source erase that is accomplished by biasing the source region at a high potential, which is about 12V, and the control gate and the substrate are grounded. The drain node is allowed to float. This causes electrons of tunneling oxide layer floats from the floating gate to the source region, which discharges or “erase” the floating gate. Under the grounded gate source erase conditions, the source bias generates significant band-to-band tunneling current, which is collected in the substrate. Because the source junction is biased near the avalanche regime, there is some multiplication of the band-to-band current. These current acts as a voltage clamp, thereby the junction voltage is limited to increase due to a voltage drop in the on-chip pass transistors. If the substrate current is sufficiently high, the hot holes are generated by the breakdown that may start to erase the memory cell. The hot holes erasing process is difficult to controls, and is avoided in well-designed memory cell.
Additionally, some holes are generated by band-to-band tunneling are trapped in the gate oxide. This may lead to erase threshold non-uniformity, speed-up of erase time with cycling, degradation of charge retention, or speed-up of gate disturb. Balanced against these negative points is the simplicity of the memory cell structure, which has led to considerable efforts to engineer junction in order to minimize the effects.
Another erase method is negative gate source erase, which is accomplished by biasing the source node at Vcc (5V) and applying approximately −10V to the control gate. In the grounded gate approach, the electrons of tunneling oxide layer float from the floating gate to the source diffusion. As a result, the memory cell is erased. The band-to-band tunneling generated holes, however, there are not heated as much as in the grounded gate case because of reduced lateral electrical field between the source region and the substrate (only 5 V at the source junction). Thus, the adverse effects from the holes are generated from the band-to-band tunneling that may be reduced. Offsetting the expected improvement in erasing performance is the additional circuit complexity that is required for the switching both positive and negative voltages by the word-line driver circuit.
Typical operation will have floating gate charged positively with respect to ground when eased and charged negatively with respect to ground when programmed. To read the memory transistor, the control gate is grounded and the gate of select transistor is biased positive voltage to provide a low resistance path from its drain contact to the drain of the memory transistor. The drain contact provides the connection to the metal bit line. The bit line is biased at a modest positive voltage (e.g. 2 volts) and the common source line is biased at ground. If the floating gate is erased, the current can flow from the bit line to the source region. If the floating gate is programmed, the memory transistor is in a non-conducting states, and there are no current flows. The presence or absence of current flow is sensed to determine the state stored by memory transistor.
The oxide in the tunnel window is typically about 10 nm thick. To program memory cell, the floating gate must be coupled to a sufficiently positive potential with respect to the drain region is of about 10 MV/cm that appears across the tunnel oxide. This is accomplished by biasing control gate at about 20 volts while biasing the select gate at a sufficiently high potential such that the select transistor is conducting with the bit line at ground potential. Under these conditions, the drain region provides a source of electrons on the cathode side of the tunneling oxide layer. With 10 MV/cm appearing across tunneling oxide layer, fowler-Nordheim tunneling occurs and charges the floating gate negatively.
To erase memory transistor, the bias across tunnel oxide must be reversed. This is accomplished by applying a high bias to drain of memory transistor while poly 2 control gate biased at ground in order to keep control gate capacitive coupled to a low voltage. The high voltage is applied to drain memory transistor by applying the desired voltage to bit line while gate of select transistor is biased at a potential that is higher than the desired voltage by at least the threshold voltage of select transistor.